Open-source driven

Chip verification,
in your browser.

Write Verilog, SystemVerilog and UVM, run it in a sandbox, and read the waveforms. Nothing to install. In early access.

Join the waitlist → Open the IDE
Runs on Icarus Verilog Verilator UVM rustdv pyuvm SVALint FCOVLint CNSTLint Verible format Surfer
What you can do
RUN

Simulate anything

Curated exercises or your own design — Icarus, Verilator, UVM. Scaffold a new one from a template with ＋ New.

CHECK

See what broke

Compile errors land in Problems, tool logs in Output, and assertion-style issues from SVALint — inline, on the line.

WAVE

Read the waveforms

Open any dump as a waveform tab, right next to your code, powered by Surfer.

Terms of use

  • An educational service, provided as-is, with no warranty.
  • Your code runs in an isolated sandbox with no network access — don't rely on it for anything sensitive.
  • Don't try to break out of the sandbox, disrupt the service, or attack others.
  • Accounts, submissions and workspace files may be reset at any time.

Privacy

  • We keep your username, optional email, and a record of your job submissions — including the IP address they came from, for abuse prevention. No third-party tracking.
  • Editor files live in your browser session only — download anything you want to keep.
  • Passwords are stored hashed; sessions use a bearer token in your browser.